1. Field of the Invention
The present invention relates to technology for non-volatile memory.
2. Description of the Related Art
Semiconductor memory devices have become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices.
Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between the source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
When programming an EEPROM or flash memory device, electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised so that the memory cell is in a programmed state. Some EEPROM and flash memory devices have a floating gate that is used to store two ranges of charges and, therefore, the memory cell can be programmed/erased between two states (an erased state and a programmed state). Such a flash memory device is sometimes referred to as a binary flash memory device. A multi-state flash memory device is implemented by identifying multiple distinct allowed/valid programmed threshold voltage ranges separated by forbidden ranges. Each distinct threshold voltage range corresponds to a predetermined value for the set of data bits encoded in the memory device. More information about programming can be found in U.S. Pat. No. 6,859,397, titled “Source Side Self Boosting Technique for Non-Volatile Memory,” and in U.S. Pat. No. 6,917,542, titled “Detecting Over Programmed Memory,” both incorporated herein by reference in their entirety.
Shifts in the apparent charge stored on a floating gate or other charge region can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates. This floating gate to floating gate coupling phenomenon is described in U.S. Pat. No. 5,867,429, which is incorporated herein by reference in its entirety. An adjacent floating gate to a target floating gate may include neighboring floating gates that are on the same bit line, neighboring floating gates on the same word line, or floating gates that are diagonal from the target floating gate because they are on both a neighboring bit line and neighboring word line.
Floating gate to floating gate coupling occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. For example, a first memory cell may be programmed to add a level of charge to its floating gate that corresponds to one set of data. Subsequently, one or more adjacent memory cells are programmed to add a level of charge to their floating gates that corresponds to a second set of data. After the one or more of the adjacent memory cells are programmed, the charge level read from the first memory cell appears to be different than programmed because of the effect of the charge on the adjacent memory cells being coupled to the first memory cell. The coupling from adjacent memory cells can shift the apparent charge level being read a sufficient amount to lead to an erroneous reading of the data stored.
The effect of floating gate to floating gate coupling is of greater concern for multi-state devices because in multi-state devices the allowed threshold voltage ranges and the forbidden ranges are narrower than in binary devices. Therefore, the floating gate to floating gate coupling can result in memory cells being shifted from an allowed threshold voltage range to a forbidden range.
In the types of memory systems described herein, as well as in others, including magnetic disc storage systems, the integrity of the data being stored is maintained by use of an error correction technique. Most commonly, an error correction code (ECC) is calculated for each sector or other unit of data that is being stored at one time, and that ECC is stored along with the data. The ECC is most commonly stored together with the sector of user data from which the ECC has been calculated. When this data is read from the memory, the ECC is used to determine the integrity of the user data being read. One or a few erroneous bits of data within a sector of data can often be corrected by use of the ECC but the existence of more errors renders the attempted data read to fail. Thus, the existence of bits that are read incorrectly because of close field coupling with adjacent memory cells can cause an attempted data read to fail.